1. Field of the Invention
The present invention relates to a video signal memory apparatus and method, and more particularly to an apparatus and method for writing and reading video signals into or from a video signal memory.
2. Description of the Prior Art
Systems for storing a composite video signal in a memory and reading out the video signal therefrom are widely used in the field of video equipment, e.g., television receivers, video tape recorders and the like. In these systems, a conventional video signal memory apparatus for a video data display device, as shown in FIG. 1, is used for writing and reading the composite video signal into or from the memory.
In FIG. 1, an input terminal 10 for receiving a composite video signal Vin (referred to hereafter as "video signal" for simplicity) is coupled to a memory controller 12 through an analog-to-digital converter (hereafter abbreviated as "A/D converter") 14. The memory controller 12 is coupled to a memory 16 through a memory data bus 18. An address data bus 20 and a mode control signal bus 22 also are provided between the memory controller 12 and the memory 16. The memory controller 12 is coupled to an output terminal 24 for supplying an output video signal Vout through a digital-to-analog converter (hereafter abbreviated as "D/A converter") 26. The memory controller 12 includes a address generator 28 comprised of a counter 30 and a timing controller 32.
The operation of the conventional video signal memory apparatus, as shown in FIG. 1, will be described hereafter. For storing the input video signal Vin in the memory 16 or reading the output video signal Vout therefrom, the following operations are carried out. The input and output video signals to or from the video signal memory apparatus are analog signals. However, signals in the video signal memory apparatus are digitally processed. Therefore, the input video signal Vin of an analog configuration is converted to a first digital video signal DV1 of a digital configuration by the A/D converter 14 prior to reaching the memory controller 12. A second digital video signal DV2 of a digital configuration read out from the memory 16 is converted to the output video signal Vout of an analog configuration by the D/A converter 26 after leaving the memory controller 12. The A/D converter 14 converts the input video signal Vin to the first digital video signal DV1 in a conventional manner. For example, the input video signal Vin is sampled repeatdly at a predetermined frequency. Each sampled value of the input video signal Vin then is digitized into the first digital video signal DV1 comprised of a predetermined number of bits, e.g., N bits. The D/A converter 26 is constructed with the same bit structure, i.e., the N bit structure of the A/D converter 14.
The counter 30 of the address generator 28 performs a count operation. A count data CD of the counter 30 is applied to the timing controller 32. The timing of the count data CD is adjusted by the timing controller 32 and the data is applied to the memory 16 as address data AD for the memory 16. The count data CD and address data AD are comprised of N bits corresponding the number of bits of the first digital video signal DV1 and the second digital video signal DV2. The counter 30 is constructed with the N bit structure for generating address data AD of N bits. The memory controller 12 supplies the memory 16 with the address data AD generated by the address generator 28 through the address data bus 20.
The memory controller 12 also supplies the memory 16 with a mode control signal W/R through the mode control signal bus 22. The mode control signal W/R takes one binary level, e.g., "1" level or another binary level, e.g., "0" level in response to the write mode or the read mode.
The first digital video signal DV1 or the second digital video signal DV2 is written into the memory 16 or read out therefrom in accordance with the address data AD. The address data AD designates addresses of the memory 16 both in the write and read modes. The counter 30 sequentially counts up the count data CD so that the count data CD, i.e., the address data AD, varies from "0 0 0 . . . 0" through a prescribed bit state, e.g., "AN AN-1 AN-2 .. A1", respectively comprised of N bit data (A represents any of digit data 1 or 0, hereafter). The counts "0 0 0 . . . 0" through "AN AN-1 AN-2 . . . A1" correspond to the addresses of the memory 16, so that the first digital video signal DV1 or the second digital video signal DV2 and the address data AD have a relationship, as shown in FIGS. 2 and 3.
The memory 16 is set to the write mode, when a mode control signal W/R of level "1" is applied to the memory 16. In the write mode, the input video signal Vin is applied to the A/D converter 14 and converted to the first digital video signal DV1 therein. The first digital video signal DV1 then is processed in the memory controller 12 so that the first digital video signal DV1 is converted to write data WD suitable for the memory 16. The write data WD is written into the memory 16 in accordance with the address data AD. At the time, the counter 30 performs the count operation so that the address data AD "0 0 0 . . . 0" through "AN AN-1 AN-2 . . . A1" are successively supplied to the memory 16 through the address data bus 20.
The memory 16 is set to the read mode, when a mode control signal W/R of level "0" is applied to the memory 16. In the read mode, read data RD is read out from the memory 16 in accordance with the address data AD. At the time, the counter 30 also performs the count operation so that the address data AD "0 0 0 . . . 0" through "AN AN-1 AN-2 . . . A1" are successively supplied to the memory 16 through the address data bus 20. The read data RD is then processed in the memory controller 12, so that the read data RD is converted to the second digital video signal DV2. The second digital video signal DV2 is applied to the D/A converter 26 and then converted therein to the output video signal Vout. The output video signal Vout is obtained on the output terminal 24.
In the conventional video signal memory apparatus, the memory stores the video signal for its entire field period. The field period includes an indicating period T1 corresponding to the displayed portion of the video signal, and a blanking period T2 corresponding to the portion of the video signal which is not displayed. In other words, the memory was provided for storing the whole video signal, including an invalid video signal in the blanking period of each field, as well as a valid video signal corresponding to the indicating period of the field. Therefore, the conventional video signal memory apparatus had to have a considerably larger memory capacity capable of storing the video signal for its whole field period. Some amount of the memory capacity corresponding to the blanking period was wasted. As a result, the effective utilization rate of the memory capacity was reduced in the conventional video signal memory apparatus.